Job Description & Details
This is a hands-on physical design role bridging the gap between logic and layout on bleeding-edge semiconductor nodes. You will be knee-deep in full RTL-to-GDSII flows, meaning you need to know how to push complex blocks through synthesis, place-and-route, and signoff without breaking timing.
What You'll Actually Be Doing
You will spend your days driving block and SoC floorplanning, running clock tree synthesis, and wrestling with timing closure across multiple corners. Unlike purely mechanical PD roles, this position demands that you actually understand logic design reports, reviewing synthesis and PNR logs to figure out why timing or logic-level optimizations are failing. You'll work closely with signoff tools to close on EMIR, IR drop, and physical verification before tapeout.
The Core Tech Stack
Your bread and butter here will be Synopsys Fusion Compiler or ICC2 for PnR and synthesis. You must be fluent in PrimeTime for static timing analysis, StarRC for extraction, and Redhawk-SC for EMIR closure. Having prior exposure to CDC, RDC, and formal verification tools like Formality ECO will immediately set you apart from other applicants.
Interview Expectations
Expect the hiring manager to hand you a scenario where a critical path is failing hold time post-route and ask you how you would fix it without blowing up your power and area targets. They want to hear about your specific buffering, sizing, and cell-swap strategies, as well as how you handle logic ECOs. They will also grill you on your advanced node experience, specifically asking how you manage routing congestion and pin access challenges at 5nm or 3nm.
Application Advice
Make sure your resume doesn't just list tools, but explicitly details your tapeout history on advanced nodes like 5nm or 3nm. Highlight keywords like Synopsys Fusion Compiler, PrimeTime, CTS, floorplanning, and timing closure right at the top so you easily clear the initial ATS screening.