Job Description & Details
This role puts you right at the intersection of design and manufacturing, where you will be building the safety nets that ensure complex SoCs actually work when they come off the wafer. If you like breaking things digitally before millions of dollars are spent on silicon spins, this is where you want to be. It is a heavy-duty technical role that requires deep familiarity with test logic and debugging elusive gate-level failures.
What You'll Actually Be Doing
You will spend your days architecting, inserting, and verifying test structures like Scan, MBIST, and Streaming Scan Network (SSN) across massive SoCs. Your time will be split between writing test plans, running ATPG pattern generation using Siemens Tessent, and chasing down regression failures in simulation. You will collaborate constantly with physical design and ATE test engineering teams to make sure the patterns you generate actually translate to clean execution on the tester floor.
The Core Tech Stack
You need absolute fluency in DFT methodologies including JTAG, IJTAG (IEEE 1687), and EDT, coupled with hands-on mastery of the Siemens Tessent suite and Synopsys synthesis tools. Beyond just running tools, you must be comfortable building SystemVerilog and UVM verification environments from scratch to validate your DFX logic. Scripting in Python, Perl, or TCL is non-negotiable here because you will be automating flows to handle massive design scales.
Interview Expectations
Expect them to hand you a scenario where a compressed scan pattern is failing on the ATE and ask you to walk through your step-by-step debug methodology from the failing cycle back to the RTL. The hiring manager is looking to see if you understand the boundary between tester constraints and internal EDT/compression logic, rather than just guessing. They will also likely drill down into how you handle clock-gating and asynchronous CDC issues within your DFX logic during synthesis.
Application Advice
Your resume needs to explicitly highlight your end-to-end experience with scan insertion, ATPG, and MBIST rather than just listing EDA tool names. Make sure to weave in keywords like Siemens Tessent, SSN, SystemVerilog, UVM, and TCL scripting so you easily clear the initial ATS filter. Emphasize any cross-functional tape-out experience where your DFX patterns directly solved a post-silicon yield issue.