Job Description & Details
This is a heavy-hitting physical design role focused on bleeding-edge semiconductor process nodes, specifically requiring hands-on experience with TSMC 2NP/3NP technology. If you are tired of legacy nodes and want to push the absolute limits of power and performance at sub-7nm, this Palo Alto-based onsite gig will keep you deep in the trenches of timing closure and physical verification.
What You'll Actually Be Doing
You will own the end-to-end physical design flow from floorplanning and power planning all the way to final signoff. Expect to spend your days knee-deep in CTS, routing, and hammering out stubborn timing violations across brutal multi-corner PVT conditions. You won't just run tools; you'll actively debug DRC/LVS violations, tackle severe routing congestion, and hunt down elusive IR drop and crosstalk issues while collaborating closely with the RTL and foundry teams.
The Core Tech Stack
You need to be fluent in industry-standard backend EDA tools like Synopsys ICC2, Fusion Compiler, or Cadence Innovus, paired with PrimeTime for static timing analysis and Calibre for physical verification. Deep mastery of UPF-based low-power design, multi-Vt strategies, and advanced power gating is non-negotiable here, alongside rock-solid Tcl, Python, or Perl scripting chops to automate your pain away.
Interview Expectations
Expect the hiring panel to grill you on your exact strategy for resolving worst-case setup and hold violations on a tight 3nm datapath, forcing you to walk through your trade-offs between buffer insertion and cell sizing. They will also probe your practical knowledge of TSMC advanced nodes, specifically asking how you handle electro-migration (EM) and dynamic IR drop bottlenecks in highly congested macro-heavy blocks.
Application Advice
Make sure your resume screams advanced node experience right at the top, explicitly calling out TSMC 2NP or 3NP if you have touched it. Ditch the generic tool lists and highlight specific tape-outs where you owned timing closure or lowered dynamic power using UPF, ensuring your application gets past the automated filters and straight to the silicon architects.