Job Description & Details
This is a heavy-hitting physical design role focused on bleeding-edge silicon nodes like TSMC 3nm and 2nm for high-performance GPUs and complex SoCs. If you like pushing EDA tools to their absolute limits and fighting marginalities at the atomic level, this gig will keep you on your toes.
What You'll Actually Be Doing
You will own the physical implementation flow from a synthesized netlist all the way to GDSII. Your day-to-day will involve hammering out complex floorplans, managing brutal routing congestion, driving clock tree synthesis, and chasing down elusive timing closure on high-frequency designs. You will constantly balance power, performance, and area (PPA) tradeoffs while dealing with severe IR drop and crosstalk issues native to sub-5nm manufacturing.
The Core Tech Stack
You need deep, battle-tested expertise in Cadence Innovus or Synopsys Fusion Compiler. Experience with TSMC's 3nm or 2nm process nodes is practically non-negotiable here, alongside signoff tools like PrimeTime for STA and Calibre for physical verification. If you haven't actually taped out chips at advanced nodes and wrestled with electromigration or advanced routing rules, you're going to struggle out of the gate.
Interview Expectations
Expect the hiring managers to drill down into your actual tape-out history, asking questions like: 'How do you specifically approach CTS and skew mitigation when dealing with massive high-frequency clock trees under severe IR drop constraints?' They want to see that you aren't just pushing buttons in Innovus, but that you fundamentally understand the device physics and equations driving the tool's algorithms. Another favorite will be walking through a real-life scenario where you hit a wall with setup/hold closure on a congested 3nm block and how you juggled Vt swapping, sizing, and routing layers to fix it.
Application Advice
Your resume needs to skip the generic project lists and explicitly highlight your tape-out track record, especially anything touching TSMC 3nm/2nm, FinFET/GAA architectures, or high-performance GPU/HPC chips. Make sure keywords like Netlist-to-GDSII, Innovus, Fusion Compiler, PrimeTime, CTS, and PPA optimization are front and center so you clear the automated screening filters immediately.